Field of the Invention: The present invention relates to integrated circuits (ICs). Particularly, there is a RAM device where digit and digit bar, defined as a pair, are laid out vertically (in the z-axis) to each other, whereas the pairs of digit lines are laid out to be parallel (in the x- or y-axis) to each other. Additionally, the vertically aligned digit line pairs allow usage of memory cells having a six square feature area (6F2) or less, where F is defined as the minimum realizable photolithographic process dimension feature size.
Dynamic random access memory (DRAM) production in the early days resulted in large chips. Manufacturing of these chips, at first, was not concerned with shrinking every part down to its smallest size. At this time the open memory array was the standard design: true digit lines on one side and complement digit (also known as digit bar or digit*) lines on the opposite side, with sense amps in the middle. However, once the DRAMS reached the 256K memory density, shrinking of all features became important.
However, to push to even higher densities, like a one Megabit density, the open architecture proved to be inadequate because of the poor signal-to-noise problem. As a result, the folded bit line architecture was developed. Yet, to use this architecture, the original memory cell from the open architecture could not be used. Thus, new cells were designed. There resulted a memory cell with a minimum size of eight square feature area (8F2). The folded architecture eliminated the signal to noise problems. Thus, further shrinkage of the other components on the DRAM resulted in an overall smaller DRAM package.
Problem
For some time now, there have been many ways developed to shrink the die size. However, a new shrinkage barrier has been reached as designs approach densities of 16 and 64 Meg chips. Every aspect of the die now has to be designed with minimal size. Thus, it is now necessary to shrink the previously acceptable eight square feature area (8F2) cells. Cell sizes of six square feature area (6F2) to four square feature area (4F2) are now needed. As a result, customers now need memory cells of six square feature area (6F2) or smaller that will also avoid the previous signal to noise ratio problems.
Note the above-described problem, as well as other problems, is solved through the subject invention and will become more apparent to one skilled in the art from the detailed description of the subject invention.